1. Field of the Invention
The present invention is generally directed to the field of data processing, and more particularly, to ensuring the existence of valid data in systems controlled by multiple clock sources.
2. State of the Art
Systems which transfer data in response to asynchronous control signals (for example, multiple asynchronous clock sources) are known. One known circuit for synchronizing data in a system which includes multiple clock sources is illustrated in FIG. 1. The FIG. 1 circuit synchronizes data which has been received at a first clock rate to a second asynchronous clock rate.
The FIG. 1 circuit is configured using two serially connected flip-flops 102 and 104. Data is supplied to the first flip-flop 102, which can be a D flip-flop, from a first time domain "A" wherein data processing is performed at a first clock rate. Data supplied to the D input of the first flip-flop is held for one clock cycle of an asynchronous output clock source associated with a second time domain "B". The data is held at the Q output of the first flip-flop 102, and then clocked into the second flip-flop 104 on the next clock pulse of clock domain B.
The one clock cycle hold time is used to resolve meta-stabilities of the input data by producing a known value at the Q output of the first flip-flop. Assuming all such meta-stabilities are resolved, the data available at the Q output of flip flop 102 is clocked into the second flip-flop 104 using the clock signal of the second, asynchronous time domain. The Q output of the second flip-flop is thereby synchronized relative to the second time domain.
While the FIG. 1 synchronizing circuit can, in most cases, provide a known value at the output of the second flip-flop in synchronism with the second clock, this circuit suffers significant drawbacks. For example, it is assumed that the first flip-flop will have correctly latched the input data and that this data is available at the time an output clock signal occurs. However, it is possible that a transition of the data input will occur before a clock pulse is received at the first flip-flop 102. As a result, it is possible that the Q output of the first flip-flop 102 will not have been resolved from a meta-stable value.
Further, the FIG. 1 synchronizing circuit is only practical for a single data line controlled by two asynchronous clocks, and is not suitable for an entire data bus. This is because the FIG. 1 circuit only provides a fixed, predetermined time delay in which meta-stabilities can be resolved. As the number of bit lines is increased, the probability that all of the bit lines will be stable within the predetermined time period is statistically reduced. Thus, attempts to use a multiplicity of flip-flops for the plural bit lines of a data bus only increase the probability that invalid data will be present at the Q outputs of the first flip-flop in each bit line. The synchronizing circuit of FIG. 1 is therefore only practical for use with a single data line and is not suitable for an entire bus of signals.
The FIG. 1 synchronizing circuit would, for example, be unsuitable for comparing an in-pointer and an asynchronous out-pointer of a first-in first-out (FIFO) memory to determine the empty or full status of the memory. In a conventional first-in first-out memory, it is desirable to compare the in-pointer with the out-pointer to determine a status of the buffer's contents. Because the data input rate to the first-in first-out memory is independent of the data output rate, a comparison of the in-pointer and the out-pointer is used to track contents of the memory.
To track the current value of an in-pointer relative to the current value of an out-pointer, the in-pointer and the out-pointer are often configured using counters. The in-pointer counter is clocked by the input data rate and the out-pointer counter is clocked by the output data rate. Current values of these two counters are repeatedly compared to determine contents of the memory. Because the two counters are clocked by different clock signals (that is, an input data rate versus an output data rate), it is possible that a counter value associated with the in-pointer and/or the out-pointer will be read in transition.
For example, it is possible that where a binary value of "3" (i.e., 011) in a counter representing the current in-pointer value is changing to a count value of "4" (i.e., 100), an invalid value of 7 (i.e., 111) will be read during the transition period of the counter. This value of 7 will, of course, lead to processing errors. These processing errors can, and do result, when the multiple signal lines of the in-pointer counter are synchronized to the time domain of the out-pointer counter using a synchronizing circuit as illustrated in FIG. 1. Again, this deficiency in operation occurs because the FIG. 1 circuit cannot ensure that data meta-stabilities in circuits which use multiple, asynchronous clocks will be resolved.
Accordingly, it would be desirable to provide a synchronizing circuit which is not dependent on a predetermined time delay, for example, the clock period of clock domain B in FIG. 1, to resolve metal-stabilities in circuits where asynchronous data rates and/or clocks are included. Further, it would be desirable to resolve such meta-stabilities in a manner suitable for synchronizing an entire data bus to multiple asynchronous clocks.